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<a href="#define-members">Macros</a> &#124;
<a href="#enum-members">Enumerations</a> &#124;
<a href="#func-members">Functions</a>  </div>
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Macros</h2></td></tr>
<tr class="memitem:gaf448568bb484f8b80052682f399f194d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csuma__api.html#gaf448568bb484f8b80052682f399f194d">XCSUDMA_WORD_SIZE</a>&#160;&#160;&#160;(4U)</td></tr>
<tr class="memdesc:gaf448568bb484f8b80052682f399f194d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transfer size conversion to bytes for Versal Net.  <a href="#gaf448568bb484f8b80052682f399f194d">More...</a><br/></td></tr>
<tr class="separator:gaf448568bb484f8b80052682f399f194d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8ee71e015a72b9441ead3a0f5541777c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csuma__api.html#ga8ee71e015a72b9441ead3a0f5541777c">XCSUDMA_H_</a></td></tr>
<tr class="memdesc:ga8ee71e015a72b9441ead3a0f5541777c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Prevent circular inclusions by using protection macros.  <a href="#ga8ee71e015a72b9441ead3a0f5541777c">More...</a><br/></td></tr>
<tr class="separator:ga8ee71e015a72b9441ead3a0f5541777c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf7ae40275005f5b2c827da41a0e3cc23"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csuma__api.html#gaf7ae40275005f5b2c827da41a0e3cc23">XCSUDMA_HW_H_</a></td></tr>
<tr class="memdesc:gaf7ae40275005f5b2c827da41a0e3cc23"><td class="mdescLeft">&#160;</td><td class="mdescRight">Prevent circular inclusions by using protection macros.  <a href="#gaf7ae40275005f5b2c827da41a0e3cc23">More...</a><br/></td></tr>
<tr class="separator:gaf7ae40275005f5b2c827da41a0e3cc23"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae02862bee946eeb9f0684d24550d1afa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csuma__api.html#gae02862bee946eeb9f0684d24550d1afa">XCsuDma_In32</a>&#160;&#160;&#160;Xil_In32</td></tr>
<tr class="memdesc:gae02862bee946eeb9f0684d24550d1afa"><td class="mdescLeft">&#160;</td><td class="mdescRight">Input operation.  <a href="#gae02862bee946eeb9f0684d24550d1afa">More...</a><br/></td></tr>
<tr class="separator:gae02862bee946eeb9f0684d24550d1afa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae5b5c8718f050b6b4e25380a92c9aa0d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csuma__api.html#gae5b5c8718f050b6b4e25380a92c9aa0d">XCsuDma_Out32</a>&#160;&#160;&#160;Xil_Out32</td></tr>
<tr class="memdesc:gae5b5c8718f050b6b4e25380a92c9aa0d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Output operation.  <a href="#gae5b5c8718f050b6b4e25380a92c9aa0d">More...</a><br/></td></tr>
<tr class="separator:gae5b5c8718f050b6b4e25380a92c9aa0d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga356d29aa2d43a1b724700007be7dcd51"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csuma__api.html#ga356d29aa2d43a1b724700007be7dcd51">XCsuDma_ReadReg</a>(BaseAddress, RegOffset)&#160;&#160;&#160;<a class="el" href="group__csuma__api.html#gae02862bee946eeb9f0684d24550d1afa">XCsuDma_In32</a>((BaseAddress) + (u32)(RegOffset))</td></tr>
<tr class="memdesc:ga356d29aa2d43a1b724700007be7dcd51"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro reads the given register.  <a href="#ga356d29aa2d43a1b724700007be7dcd51">More...</a><br/></td></tr>
<tr class="separator:ga356d29aa2d43a1b724700007be7dcd51"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5a2390fe93e02061d01c3b9e057b3b2b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csuma__api.html#ga5a2390fe93e02061d01c3b9e057b3b2b">XCsuDma_WriteReg</a>(BaseAddress, RegOffset, Data)&#160;&#160;&#160;<a class="el" href="group__csuma__api.html#gae5b5c8718f050b6b4e25380a92c9aa0d">XCsuDma_Out32</a>((BaseAddress) + (u32)(RegOffset), (u32)(Data))</td></tr>
<tr class="memdesc:ga5a2390fe93e02061d01c3b9e057b3b2b"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro writes the value into the given register.  <a href="#ga5a2390fe93e02061d01c3b9e057b3b2b">More...</a><br/></td></tr>
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Enumerations</h2></td></tr>
<tr class="memitem:ga46008337fdd632f2650b8727c305eba5"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csuma__api.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a> { <a class="el" href="group__csuma__api.html#gga46008337fdd632f2650b8727c305eba5afe0a7c4c64751afddad37c4a15a00e0d">XCSUDMA_SRC_CHANNEL</a> = 0U, 
<a class="el" href="group__csuma__api.html#gga46008337fdd632f2650b8727c305eba5a08d300b013b7169bd1475fdf04737fe4">XCSUDMA_DST_CHANNEL</a>
 }</td></tr>
<tr class="memdesc:ga46008337fdd632f2650b8727c305eba5"><td class="mdescLeft">&#160;</td><td class="mdescRight">This typedef contains CSU_DMA Channel Types.  <a href="group__csuma__api.html#ga46008337fdd632f2650b8727c305eba5">More...</a><br/></td></tr>
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Functions</h2></td></tr>
<tr class="memitem:gad0f7217bd295de82623179efb34adb96"><td class="memItemLeft" align="right" valign="top">s32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csuma__api.html#gad0f7217bd295de82623179efb34adb96">XCsuDma_CfgInitialize</a> (<a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *InstancePtr, <a class="el" href="struct_x_csu_dma___config.html">XCsuDma_Config</a> *CfgPtr, UINTPTR EffectiveAddr)</td></tr>
<tr class="memdesc:gad0f7217bd295de82623179efb34adb96"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function initializes CSU_DMA core.  <a href="#gad0f7217bd295de82623179efb34adb96">More...</a><br/></td></tr>
<tr class="separator:gad0f7217bd295de82623179efb34adb96"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacf79144df19e9cd4116dd9f507037ff1"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csuma__api.html#gacf79144df19e9cd4116dd9f507037ff1">XCsuDma_Transfer</a> (<a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *InstancePtr, <a class="el" href="group__csuma__api.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a> Channel, u64 Addr, u32 Size, u8 EnDataLast)</td></tr>
<tr class="memdesc:gacf79144df19e9cd4116dd9f507037ff1"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the starting address and size of the data to be transferred from/to the memory through the AXI interface.  <a href="#gacf79144df19e9cd4116dd9f507037ff1">More...</a><br/></td></tr>
<tr class="separator:gacf79144df19e9cd4116dd9f507037ff1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga83a1043112b6067b1901d2bdcb29563d"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csuma__api.html#ga83a1043112b6067b1901d2bdcb29563d">XCsuDma_64BitTransfer</a> (<a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *InstancePtr, <a class="el" href="group__csuma__api.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a> Channel, u32 AddrLow, u32 AddrHigh, u32 Size, u8 EnDataLast)</td></tr>
<tr class="memdesc:ga83a1043112b6067b1901d2bdcb29563d"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the starting address and size of the data to be transferred from/to the memory through the AXI interface.  <a href="#ga83a1043112b6067b1901d2bdcb29563d">More...</a><br/></td></tr>
<tr class="separator:ga83a1043112b6067b1901d2bdcb29563d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga25049be545d8ec6eae2426b6248a8e4f"><td class="memItemLeft" align="right" valign="top">u64&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csuma__api.html#ga25049be545d8ec6eae2426b6248a8e4f">XCsuDma_GetAddr</a> (<a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *InstancePtr, <a class="el" href="group__csuma__api.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a> Channel)</td></tr>
<tr class="memdesc:ga25049be545d8ec6eae2426b6248a8e4f"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function returns the current address location of the memory, from where it has to read the data(SRC) or the location where it has to write the data (DST) based on the channel selection.  <a href="#ga25049be545d8ec6eae2426b6248a8e4f">More...</a><br/></td></tr>
<tr class="separator:ga25049be545d8ec6eae2426b6248a8e4f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad5fd579fb9c166e59ee1f9d3b39250c7"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csuma__api.html#gad5fd579fb9c166e59ee1f9d3b39250c7">XCsuDma_GetSize</a> (<a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *InstancePtr, <a class="el" href="group__csuma__api.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a> Channel)</td></tr>
<tr class="memdesc:gad5fd579fb9c166e59ee1f9d3b39250c7"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function returns the size of the data yet to be transferred from memory to CSU_DMA or CSU_DMA to memory based on the channel selection.  <a href="#gad5fd579fb9c166e59ee1f9d3b39250c7">More...</a><br/></td></tr>
<tr class="separator:gad5fd579fb9c166e59ee1f9d3b39250c7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga00b5080126710866186d0bfafd26e9b6"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csuma__api.html#ga00b5080126710866186d0bfafd26e9b6">XCsuDma_Pause</a> (<a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *InstancePtr, <a class="el" href="group__csuma__api.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a> Channel, <a class="el" href="xcsudma_8h.html#ad5ce08d197288cbdfb06941f1d46df87">XCsuDma_PauseType</a> Type)</td></tr>
<tr class="memdesc:ga00b5080126710866186d0bfafd26e9b6"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function pauses the Channel data transfer to/from memory or to/from stream based on pause type.  <a href="#ga00b5080126710866186d0bfafd26e9b6">More...</a><br/></td></tr>
<tr class="separator:ga00b5080126710866186d0bfafd26e9b6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa3450f812658f927f289b997b12a4174"><td class="memItemLeft" align="right" valign="top">s32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csuma__api.html#gaa3450f812658f927f289b997b12a4174">XCsuDma_IsPaused</a> (<a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *InstancePtr, <a class="el" href="group__csuma__api.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a> Channel, <a class="el" href="xcsudma_8h.html#ad5ce08d197288cbdfb06941f1d46df87">XCsuDma_PauseType</a> Type)</td></tr>
<tr class="memdesc:gaa3450f812658f927f289b997b12a4174"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function checks whether Channel memory/stream is paused based on the given pause type.  <a href="#gaa3450f812658f927f289b997b12a4174">More...</a><br/></td></tr>
<tr class="separator:gaa3450f812658f927f289b997b12a4174"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaeee3f2d5bcf265b57c9f214f2bc15a28"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csuma__api.html#gaeee3f2d5bcf265b57c9f214f2bc15a28">XCsuDma_Resume</a> (<a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *InstancePtr, <a class="el" href="group__csuma__api.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a> Channel, <a class="el" href="xcsudma_8h.html#ad5ce08d197288cbdfb06941f1d46df87">XCsuDma_PauseType</a> Type)</td></tr>
<tr class="memdesc:gaeee3f2d5bcf265b57c9f214f2bc15a28"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function resumes the channel if it is in paused state and continues where it has left.  <a href="#gaeee3f2d5bcf265b57c9f214f2bc15a28">More...</a><br/></td></tr>
<tr class="separator:gaeee3f2d5bcf265b57c9f214f2bc15a28"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga17f1a7ba935f4bf3626050e0b0e0142b"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csuma__api.html#ga17f1a7ba935f4bf3626050e0b0e0142b">XCsuDma_GetCheckSum</a> (<a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *InstancePtr)</td></tr>
<tr class="memdesc:ga17f1a7ba935f4bf3626050e0b0e0142b"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function returns the sum of all the data read from AXI memory.  <a href="#ga17f1a7ba935f4bf3626050e0b0e0142b">More...</a><br/></td></tr>
<tr class="separator:ga17f1a7ba935f4bf3626050e0b0e0142b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga78bdd79674e2b5c92b9701cacfde1fe1"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csuma__api.html#ga78bdd79674e2b5c92b9701cacfde1fe1">XCsuDma_ClearCheckSum</a> (<a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *InstancePtr)</td></tr>
<tr class="memdesc:ga78bdd79674e2b5c92b9701cacfde1fe1"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function clears the check sum of the data read from AXI memory.  <a href="#ga78bdd79674e2b5c92b9701cacfde1fe1">More...</a><br/></td></tr>
<tr class="separator:ga78bdd79674e2b5c92b9701cacfde1fe1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga73867b4acb189982642e4c1ae4f92fb9"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csuma__api.html#ga73867b4acb189982642e4c1ae4f92fb9">XCsuDma_WaitForDoneTimeout</a> (<a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *InstancePtr, <a class="el" href="group__csuma__api.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a> Channel)</td></tr>
<tr class="memdesc:ga73867b4acb189982642e4c1ae4f92fb9"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function polls for completion of data transfer periodically until the DMA done bit set or until the timeout occurs.  <a href="#ga73867b4acb189982642e4c1ae4f92fb9">More...</a><br/></td></tr>
<tr class="separator:ga73867b4acb189982642e4c1ae4f92fb9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac9b6265e467b03cc903cd66781e95e63"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csuma__api.html#gac9b6265e467b03cc903cd66781e95e63">XCsuDma_SetConfig</a> (<a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *InstancePtr, <a class="el" href="group__csuma__api.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a> Channel, <a class="el" href="struct_x_csu_dma___configure.html">XCsuDma_Configure</a> *ConfigurValues)</td></tr>
<tr class="memdesc:gac9b6265e467b03cc903cd66781e95e63"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function configures all the values of CSU_DMA Channels with the values of updated <a class="el" href="struct_x_csu_dma___configure.html" title="This typedef contains all the configuration feilds which must be set before the start of the data tra...">XCsuDma_Configure</a> structure.  <a href="#gac9b6265e467b03cc903cd66781e95e63">More...</a><br/></td></tr>
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<tr class="memitem:gaab0b66bca3f38d26d38ff47544fa6b11"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csuma__api.html#gaab0b66bca3f38d26d38ff47544fa6b11">XCsuDma_GetConfig</a> (<a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *InstancePtr, <a class="el" href="group__csuma__api.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a> Channel, <a class="el" href="struct_x_csu_dma___configure.html">XCsuDma_Configure</a> *ConfigurValues)</td></tr>
<tr class="memdesc:gaab0b66bca3f38d26d38ff47544fa6b11"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function updates <a class="el" href="struct_x_csu_dma___configure.html" title="This typedef contains all the configuration feilds which must be set before the start of the data tra...">XCsuDma_Configure</a> structure members with the configured values of CSU_DMA's Channel.  <a href="#gaab0b66bca3f38d26d38ff47544fa6b11">More...</a><br/></td></tr>
<tr class="separator:gaab0b66bca3f38d26d38ff47544fa6b11"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6169fa380a4d55e41d7ab96589372e8f"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csuma__api.html#ga6169fa380a4d55e41d7ab96589372e8f">XCsuDma_IntrGetStatus</a> (<a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *InstancePtr, <a class="el" href="group__csuma__api.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a> Channel)</td></tr>
<tr class="memdesc:ga6169fa380a4d55e41d7ab96589372e8f"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function returns interrupt status read from Interrupt Status Register.  <a href="#ga6169fa380a4d55e41d7ab96589372e8f">More...</a><br/></td></tr>
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<tr class="memitem:ga1db5eabd96920efb06fb03c919420601"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csuma__api.html#ga1db5eabd96920efb06fb03c919420601">XCsuDma_IntrClear</a> (<a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *InstancePtr, <a class="el" href="group__csuma__api.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a> Channel, u32 Mask)</td></tr>
<tr class="memdesc:ga1db5eabd96920efb06fb03c919420601"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function clears interrupt(s).  <a href="#ga1db5eabd96920efb06fb03c919420601">More...</a><br/></td></tr>
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<tr class="memitem:gad892a65e65ac14f48f7d7f53020511cf"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csuma__api.html#gad892a65e65ac14f48f7d7f53020511cf">XCsuDma_EnableIntr</a> (<a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *InstancePtr, <a class="el" href="group__csuma__api.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a> Channel, u32 Mask)</td></tr>
<tr class="memdesc:gad892a65e65ac14f48f7d7f53020511cf"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function enables the interrupt(s).  <a href="#gad892a65e65ac14f48f7d7f53020511cf">More...</a><br/></td></tr>
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<tr class="memitem:gadf3599e4d07ef05586a217ebbbd02999"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csuma__api.html#gadf3599e4d07ef05586a217ebbbd02999">XCsuDma_DisableIntr</a> (<a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *InstancePtr, <a class="el" href="group__csuma__api.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a> Channel, u32 Mask)</td></tr>
<tr class="memdesc:gadf3599e4d07ef05586a217ebbbd02999"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function disables the interrupt(s).  <a href="#gadf3599e4d07ef05586a217ebbbd02999">More...</a><br/></td></tr>
<tr class="separator:gadf3599e4d07ef05586a217ebbbd02999"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6ed420e8bfd9ab489a2d2c3e984ca7a2"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csuma__api.html#ga6ed420e8bfd9ab489a2d2c3e984ca7a2">XCsuDma_GetIntrMask</a> (<a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *InstancePtr, <a class="el" href="group__csuma__api.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a> Channel)</td></tr>
<tr class="memdesc:ga6ed420e8bfd9ab489a2d2c3e984ca7a2"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function returns the interrupt mask to know which interrupts are enabled and which of them were disaled.  <a href="#ga6ed420e8bfd9ab489a2d2c3e984ca7a2">More...</a><br/></td></tr>
<tr class="separator:ga6ed420e8bfd9ab489a2d2c3e984ca7a2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga774ab551d0ef59fd880ff834f2d83804"><td class="memItemLeft" align="right" valign="top">s32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csuma__api.html#ga774ab551d0ef59fd880ff834f2d83804">XCsuDma_SelfTest</a> (<a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *InstancePtr)</td></tr>
<tr class="memdesc:ga774ab551d0ef59fd880ff834f2d83804"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function runs a self-test on the driver and hardware device.  <a href="#ga774ab551d0ef59fd880ff834f2d83804">More...</a><br/></td></tr>
<tr class="separator:ga774ab551d0ef59fd880ff834f2d83804"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9b921be4bb07b632d2dfd8ac34c30fb8"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_csu_dma___config.html">XCsuDma_Config</a> *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csuma__api.html#ga9b921be4bb07b632d2dfd8ac34c30fb8">XCsuDma_LookupConfig</a> (u16 DeviceId)</td></tr>
<tr class="memdesc:ga9b921be4bb07b632d2dfd8ac34c30fb8"><td class="mdescLeft">&#160;</td><td class="mdescRight">XCsuDma_LookupConfig returns a reference to an <a class="el" href="struct_x_csu_dma___config.html" title="This typedef contains configuration information for a CSU_DMA core. ">XCsuDma_Config</a> structure based on the unique device id, <em>DeviceId</em>.  <a href="#ga9b921be4bb07b632d2dfd8ac34c30fb8">More...</a><br/></td></tr>
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Registers offsets</h2></td></tr>
<tr class="memitem:ga76fcd0f2a0c7ebc2058f231a944c7109"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csuma__api.html#ga76fcd0f2a0c7ebc2058f231a944c7109">XCSUDMA_ADDR_OFFSET</a>&#160;&#160;&#160;0x000U</td></tr>
<tr class="memdesc:ga76fcd0f2a0c7ebc2058f231a944c7109"><td class="mdescLeft">&#160;</td><td class="mdescRight">Address Register Offset.  <a href="#ga76fcd0f2a0c7ebc2058f231a944c7109">More...</a><br/></td></tr>
<tr class="separator:ga76fcd0f2a0c7ebc2058f231a944c7109"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf5d3e01cba7a5d0029901f690007a9c0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csuma__api.html#gaf5d3e01cba7a5d0029901f690007a9c0">XCSUDMA_SIZE_OFFSET</a>&#160;&#160;&#160;0x004U</td></tr>
<tr class="memdesc:gaf5d3e01cba7a5d0029901f690007a9c0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Size Register Offset.  <a href="#gaf5d3e01cba7a5d0029901f690007a9c0">More...</a><br/></td></tr>
<tr class="separator:gaf5d3e01cba7a5d0029901f690007a9c0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa69407558163d5fc58ac9621b3e313a3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csuma__api.html#gaa69407558163d5fc58ac9621b3e313a3">XCSUDMA_STS_OFFSET</a>&#160;&#160;&#160;0x008U</td></tr>
<tr class="memdesc:gaa69407558163d5fc58ac9621b3e313a3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Status Register Offset.  <a href="#gaa69407558163d5fc58ac9621b3e313a3">More...</a><br/></td></tr>
<tr class="separator:gaa69407558163d5fc58ac9621b3e313a3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga60d1ed5209af6a5d9e9c55b6b95052de"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csuma__api.html#ga60d1ed5209af6a5d9e9c55b6b95052de">XCSUDMA_CTRL_OFFSET</a>&#160;&#160;&#160;0x00CU</td></tr>
<tr class="memdesc:ga60d1ed5209af6a5d9e9c55b6b95052de"><td class="mdescLeft">&#160;</td><td class="mdescRight">Control Register Offset.  <a href="#ga60d1ed5209af6a5d9e9c55b6b95052de">More...</a><br/></td></tr>
<tr class="separator:ga60d1ed5209af6a5d9e9c55b6b95052de"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab56adb100901bb2b042a842619064ce5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csuma__api.html#gab56adb100901bb2b042a842619064ce5">XCSUDMA_I_STS_OFFSET</a>&#160;&#160;&#160;0x014U</td></tr>
<tr class="memdesc:gab56adb100901bb2b042a842619064ce5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Status Register Offset.  <a href="#gab56adb100901bb2b042a842619064ce5">More...</a><br/></td></tr>
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Size register bit masks and shifts</h2></td></tr>
<tr class="memitem:ga2e9db5623d0c9b85088c528d43c9b411"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csuma__api.html#ga2e9db5623d0c9b85088c528d43c9b411">XCSUDMA_SIZE_MASK</a>&#160;&#160;&#160;0x1FFFFFFCU</td></tr>
<tr class="memdesc:ga2e9db5623d0c9b85088c528d43c9b411"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mask for size.  <a href="#ga2e9db5623d0c9b85088c528d43c9b411">More...</a><br/></td></tr>
<tr class="separator:ga2e9db5623d0c9b85088c528d43c9b411"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf0a5114bb4e675c0e9d933a2d235ac6f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csuma__api.html#gaf0a5114bb4e675c0e9d933a2d235ac6f">XCSUDMA_LAST_WORD_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:gaf0a5114bb4e675c0e9d933a2d235ac6f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Last word check bit mask.  <a href="#gaf0a5114bb4e675c0e9d933a2d235ac6f">More...</a><br/></td></tr>
<tr class="separator:gaf0a5114bb4e675c0e9d933a2d235ac6f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae1d5689d4fbd05c2e7f6b2a34bcbfb09"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csuma__api.html#gae1d5689d4fbd05c2e7f6b2a34bcbfb09">XCSUDMA_SIZE_SHIFT</a>&#160;&#160;&#160;2U</td></tr>
<tr class="memdesc:gae1d5689d4fbd05c2e7f6b2a34bcbfb09"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift for size.  <a href="#gae1d5689d4fbd05c2e7f6b2a34bcbfb09">More...</a><br/></td></tr>
<tr class="separator:gae1d5689d4fbd05c2e7f6b2a34bcbfb09"><td class="memSeparator" colspan="2">&#160;</td></tr>
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Interrupt Enable/Disable/Mask/Status registers bit masks</h2></td></tr>
<tr class="memitem:ga33dc1a1076170c9ca47df1c3451bdfe5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csuma__api.html#ga33dc1a1076170c9ca47df1c3451bdfe5">XCSUDMA_IXR_FIFO_OVERFLOW_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:ga33dc1a1076170c9ca47df1c3451bdfe5"><td class="mdescLeft">&#160;</td><td class="mdescRight">FIFO overflow mask, it is valid only to Destination Channel.  <a href="#ga33dc1a1076170c9ca47df1c3451bdfe5">More...</a><br/></td></tr>
<tr class="separator:ga33dc1a1076170c9ca47df1c3451bdfe5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6e7d15f2dfaa7afef685f382db12c62e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csuma__api.html#ga6e7d15f2dfaa7afef685f382db12c62e">XCSUDMA_IXR_INVALID_APB_MASK</a>&#160;&#160;&#160;0x00000040U</td></tr>
<tr class="memdesc:ga6e7d15f2dfaa7afef685f382db12c62e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Invalid APB access mask.  <a href="#ga6e7d15f2dfaa7afef685f382db12c62e">More...</a><br/></td></tr>
<tr class="separator:ga6e7d15f2dfaa7afef685f382db12c62e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf727ccf4d9bbbce46d61f67be041b40c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csuma__api.html#gaf727ccf4d9bbbce46d61f67be041b40c">XCSUDMA_IXR_FIFO_THRESHHIT_MASK</a>&#160;&#160;&#160;0x00000020U</td></tr>
<tr class="memdesc:gaf727ccf4d9bbbce46d61f67be041b40c"><td class="mdescLeft">&#160;</td><td class="mdescRight">FIFO threshold hit indicator mask.  <a href="#gaf727ccf4d9bbbce46d61f67be041b40c">More...</a><br/></td></tr>
<tr class="separator:gaf727ccf4d9bbbce46d61f67be041b40c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadb917cad64699bd0fc6e21c1fec74068"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csuma__api.html#gadb917cad64699bd0fc6e21c1fec74068">XCSUDMA_IXR_TIMEOUT_MEM_MASK</a>&#160;&#160;&#160;0x00000010U</td></tr>
<tr class="memdesc:gadb917cad64699bd0fc6e21c1fec74068"><td class="mdescLeft">&#160;</td><td class="mdescRight">Time out counter expired to access memory mask.  <a href="#gadb917cad64699bd0fc6e21c1fec74068">More...</a><br/></td></tr>
<tr class="separator:gadb917cad64699bd0fc6e21c1fec74068"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7fc13f5152cf0098d76d4b78b08702e8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csuma__api.html#ga7fc13f5152cf0098d76d4b78b08702e8">XCSUDMA_IXR_TIMEOUT_STRM_MASK</a>&#160;&#160;&#160;0x00000008U</td></tr>
<tr class="memdesc:ga7fc13f5152cf0098d76d4b78b08702e8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Time out counter expired to access stream mask.  <a href="#ga7fc13f5152cf0098d76d4b78b08702e8">More...</a><br/></td></tr>
<tr class="separator:ga7fc13f5152cf0098d76d4b78b08702e8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac6e2bc9f25b7160249710c395a74d933"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csuma__api.html#gac6e2bc9f25b7160249710c395a74d933">XCSUDMA_IXR_AXI_WRERR_MASK</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:gac6e2bc9f25b7160249710c395a74d933"><td class="mdescLeft">&#160;</td><td class="mdescRight">AXI Read/Write error mask.  <a href="#gac6e2bc9f25b7160249710c395a74d933">More...</a><br/></td></tr>
<tr class="separator:gac6e2bc9f25b7160249710c395a74d933"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0dbd333c70de601e769b8542552eb7e4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csuma__api.html#ga0dbd333c70de601e769b8542552eb7e4">XCSUDMA_IXR_DONE_MASK</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:ga0dbd333c70de601e769b8542552eb7e4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Done mask.  <a href="#ga0dbd333c70de601e769b8542552eb7e4">More...</a><br/></td></tr>
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<tr class="memitem:ga670d9fac28bd9de6b6f6abcb5fda64cc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csuma__api.html#ga670d9fac28bd9de6b6f6abcb5fda64cc">XCSUDMA_IXR_MEM_DONE_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:ga670d9fac28bd9de6b6f6abcb5fda64cc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Memory done mask, it is valid only for source channel.  <a href="#ga670d9fac28bd9de6b6f6abcb5fda64cc">More...</a><br/></td></tr>
<tr class="separator:ga670d9fac28bd9de6b6f6abcb5fda64cc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga441edc2ec9eadb8093ac0ab41e0162d2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csuma__api.html#ga441edc2ec9eadb8093ac0ab41e0162d2">XCSUDMA_IXR_SRC_MASK</a>&#160;&#160;&#160;0x0000007FU</td></tr>
<tr class="memdesc:ga441edc2ec9eadb8093ac0ab41e0162d2"><td class="mdescLeft">&#160;</td><td class="mdescRight"><pre class="fragment"> ((XCSUDMA_IXR_INVALID_APB_MASK)|
</pre><p> (XCSUDMA_IXR_FIFO_THRESHHIT_MASK) | (XCSUDMA_IXR_TIMEOUT_MEM_MASK) | (XCSUDMA_IXR_TIMEOUT_STRM_MASK) | (XCSUDMA_IXR_AXI_WRERR_MASK) | (XCSUDMA_IXR_DONE_MASK) | (XCSUDMA_IXR_MEM_DONE_MASK))  <a href="#ga441edc2ec9eadb8093ac0ab41e0162d2">More...</a><br/></td></tr>
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<tr class="memitem:gadfb7ef2922c9ceb4804bc87620c35134"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csuma__api.html#gadfb7ef2922c9ceb4804bc87620c35134">XCSUDMA_IXR_DST_MASK</a>&#160;&#160;&#160;0x000000FEU</td></tr>
<tr class="memdesc:gadfb7ef2922c9ceb4804bc87620c35134"><td class="mdescLeft">&#160;</td><td class="mdescRight"><pre class="fragment"> ((XCSUDMA_IXR_FIFO_OVERFLOW_MASK) |
</pre><p> (XCSUDMA_IXR_INVALID_APB_MASK) | (XCSUDMA_IXR_FIFO_THRESHHIT_MASK) | (XCSUDMA_IXR_TIMEOUT_MEM_MASK) | (XCSUDMA_IXR_TIMEOUT_STRM_MASK) | (XCSUDMA_IXR_AXI_WRERR_MASK) | (XCSUDMA_IXR_DONE_MASK))  <a href="#gadfb7ef2922c9ceb4804bc87620c35134">More...</a><br/></td></tr>
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
Software done timeout value</h2></td></tr>
<tr class="memitem:ga0bd0c9763013ce910920b46ad35d10ba"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csuma__api.html#ga0bd0c9763013ce910920b46ad35d10ba">XCSUDMA_DONE_TIMEOUT_VAL</a>&#160;&#160;&#160;300000000U</td></tr>
<tr class="memdesc:ga0bd0c9763013ce910920b46ad35d10ba"><td class="mdescLeft">&#160;</td><td class="mdescRight">SW timeout loop value for transfer completion.  <a href="#ga0bd0c9763013ce910920b46ad35d10ba">More...</a><br/></td></tr>
<tr class="separator:ga0bd0c9763013ce910920b46ad35d10ba"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<h2 class="groupheader">Macro Definition Documentation</h2>
<a class="anchor" id="ga76fcd0f2a0c7ebc2058f231a944c7109"></a>
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          <td class="memname">#define XCSUDMA_ADDR_OFFSET&#160;&#160;&#160;0x000U</td>
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<p>Address Register Offset. </p>

<p>Referenced by <a class="el" href="group__csuma__api.html#ga83a1043112b6067b1901d2bdcb29563d">XCsuDma_64BitTransfer()</a>, <a class="el" href="group__csuma__api.html#ga25049be545d8ec6eae2426b6248a8e4f">XCsuDma_GetAddr()</a>, and <a class="el" href="group__csuma__api.html#gacf79144df19e9cd4116dd9f507037ff1">XCsuDma_Transfer()</a>.</p>

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          <td class="memname">#define XCSUDMA_CTRL_OFFSET&#160;&#160;&#160;0x00CU</td>
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      </table>
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<p>Control Register Offset. </p>

<p>Referenced by <a class="el" href="group__csuma__api.html#gaab0b66bca3f38d26d38ff47544fa6b11">XCsuDma_GetConfig()</a>, <a class="el" href="group__csuma__api.html#gaa3450f812658f927f289b997b12a4174">XCsuDma_IsPaused()</a>, <a class="el" href="group__csuma__api.html#ga00b5080126710866186d0bfafd26e9b6">XCsuDma_Pause()</a>, <a class="el" href="group__csuma__api.html#gaeee3f2d5bcf265b57c9f214f2bc15a28">XCsuDma_Resume()</a>, <a class="el" href="group__csuma__api.html#ga774ab551d0ef59fd880ff834f2d83804">XCsuDma_SelfTest()</a>, and <a class="el" href="group__csuma__api.html#gac9b6265e467b03cc903cd66781e95e63">XCsuDma_SetConfig()</a>.</p>

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<a class="anchor" id="ga0bd0c9763013ce910920b46ad35d10ba"></a>
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          <td class="memname">#define XCSUDMA_DONE_TIMEOUT_VAL&#160;&#160;&#160;300000000U</td>
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<p>SW timeout loop value for transfer completion. </p>

<p>Referenced by <a class="el" href="group__csuma__api.html#ga73867b4acb189982642e4c1ae4f92fb9">XCsuDma_WaitForDoneTimeout()</a>.</p>

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          <td class="memname">#define XCSUDMA_H_</td>
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<p>Prevent circular inclusions by using protection macros. </p>

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<a class="anchor" id="gaf7ae40275005f5b2c827da41a0e3cc23"></a>
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          <td class="memname">#define XCSUDMA_HW_H_</td>
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<p>Prevent circular inclusions by using protection macros. </p>

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          <td class="memname">#define XCSUDMA_I_STS_OFFSET&#160;&#160;&#160;0x014U</td>
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<p>Interrupt Status Register Offset. </p>

<p>Referenced by <a class="el" href="group__csuma__api.html#ga1db5eabd96920efb06fb03c919420601">XCsuDma_IntrClear()</a>, <a class="el" href="group__csuma__api.html#ga6169fa380a4d55e41d7ab96589372e8f">XCsuDma_IntrGetStatus()</a>, and <a class="el" href="group__csuma__api.html#ga73867b4acb189982642e4c1ae4f92fb9">XCsuDma_WaitForDoneTimeout()</a>.</p>

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          <td class="memname">#define XCsuDma_In32&#160;&#160;&#160;Xil_In32</td>
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<p>Input operation. </p>

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          <td class="memname">#define XCSUDMA_IXR_AXI_WRERR_MASK&#160;&#160;&#160;0x00000004U</td>
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<p>AXI Read/Write error mask. </p>

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          <td class="memname">#define XCSUDMA_IXR_DONE_MASK&#160;&#160;&#160;0x00000002U</td>
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<p>Done mask. </p>

<p>Referenced by <a class="el" href="xcsudma__intr__example_8c.html#ae07b94c3ade7479c4ec8dfec3bb4d643">XCsuDma_IntrExample()</a>, <a class="el" href="xcsudma__polled__example_8c.html#aff327ee48af8d9e5c4018dd4e463674c">XCsuDma_PolledExample()</a>, and <a class="el" href="group__csuma__api.html#ga73867b4acb189982642e4c1ae4f92fb9">XCsuDma_WaitForDoneTimeout()</a>.</p>

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          <td class="memname">#define XCSUDMA_IXR_DST_MASK&#160;&#160;&#160;0x000000FEU</td>
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<p><pre class="fragment"> ((XCSUDMA_IXR_FIFO_OVERFLOW_MASK) |
</pre><p> (XCSUDMA_IXR_INVALID_APB_MASK) | (XCSUDMA_IXR_FIFO_THRESHHIT_MASK) | (XCSUDMA_IXR_TIMEOUT_MEM_MASK) | (XCSUDMA_IXR_TIMEOUT_STRM_MASK) | (XCSUDMA_IXR_AXI_WRERR_MASK) | (XCSUDMA_IXR_DONE_MASK)) </p>
<p>All interrupt mask for destination </p>

<p>Referenced by <a class="el" href="group__csuma__api.html#gadf3599e4d07ef05586a217ebbbd02999">XCsuDma_DisableIntr()</a>, <a class="el" href="group__csuma__api.html#gad892a65e65ac14f48f7d7f53020511cf">XCsuDma_EnableIntr()</a>, and <a class="el" href="group__csuma__api.html#ga1db5eabd96920efb06fb03c919420601">XCsuDma_IntrClear()</a>.</p>

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          <td class="memname">#define XCSUDMA_IXR_FIFO_OVERFLOW_MASK&#160;&#160;&#160;0x00000001U</td>
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<p>FIFO overflow mask, it is valid only to Destination Channel. </p>

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          <td class="memname">#define XCSUDMA_IXR_FIFO_THRESHHIT_MASK&#160;&#160;&#160;0x00000020U</td>
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<p>FIFO threshold hit indicator mask. </p>

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          <td class="memname">#define XCSUDMA_IXR_INVALID_APB_MASK&#160;&#160;&#160;0x00000040U</td>
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<p>Invalid APB access mask. </p>

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          <td class="memname">#define XCSUDMA_IXR_MEM_DONE_MASK&#160;&#160;&#160;0x00000001U</td>
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<p>Memory done mask, it is valid only for source channel. </p>

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          <td class="memname">#define XCSUDMA_IXR_SRC_MASK&#160;&#160;&#160;0x0000007FU</td>
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<p><pre class="fragment"> ((XCSUDMA_IXR_INVALID_APB_MASK)|
</pre><p> (XCSUDMA_IXR_FIFO_THRESHHIT_MASK) | (XCSUDMA_IXR_TIMEOUT_MEM_MASK) | (XCSUDMA_IXR_TIMEOUT_STRM_MASK) | (XCSUDMA_IXR_AXI_WRERR_MASK) | (XCSUDMA_IXR_DONE_MASK) | (XCSUDMA_IXR_MEM_DONE_MASK)) </p>
<p>All interrupt mask for source </p>

<p>Referenced by <a class="el" href="group__csuma__api.html#gadf3599e4d07ef05586a217ebbbd02999">XCsuDma_DisableIntr()</a>, <a class="el" href="group__csuma__api.html#gad892a65e65ac14f48f7d7f53020511cf">XCsuDma_EnableIntr()</a>, and <a class="el" href="group__csuma__api.html#ga1db5eabd96920efb06fb03c919420601">XCsuDma_IntrClear()</a>.</p>

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<a class="anchor" id="gadb917cad64699bd0fc6e21c1fec74068"></a>
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          <td class="memname">#define XCSUDMA_IXR_TIMEOUT_MEM_MASK&#160;&#160;&#160;0x00000010U</td>
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<p>Time out counter expired to access memory mask. </p>

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          <td class="memname">#define XCSUDMA_IXR_TIMEOUT_STRM_MASK&#160;&#160;&#160;0x00000008U</td>
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<p>Time out counter expired to access stream mask. </p>

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          <td class="memname">#define XCSUDMA_LAST_WORD_MASK&#160;&#160;&#160;0x00000001U</td>
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<p>Last word check bit mask. </p>

<p>Referenced by <a class="el" href="group__csuma__api.html#ga83a1043112b6067b1901d2bdcb29563d">XCsuDma_64BitTransfer()</a>, and <a class="el" href="group__csuma__api.html#gacf79144df19e9cd4116dd9f507037ff1">XCsuDma_Transfer()</a>.</p>

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          <td class="memname">#define XCsuDma_Out32&#160;&#160;&#160;Xil_Out32</td>
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<p>Output operation. </p>

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          <td class="memname">#define XCsuDma_ReadReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;<a class="el" href="group__csuma__api.html#gae02862bee946eeb9f0684d24550d1afa">XCsuDma_In32</a>((BaseAddress) + (u32)(RegOffset))</td>
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<p>This macro reads the given register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>Base address of the CSU_DMA core. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>Register offset of the register.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The 32-bit value of the register.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group__csuma__api.html#ga356d29aa2d43a1b724700007be7dcd51" title="This macro reads the given register. ">XCsuDma_ReadReg(u32 BaseAddress, u32 RegOffset)</a> </dd></dl>

<p>Referenced by <a class="el" href="group__csuma__api.html#ga25049be545d8ec6eae2426b6248a8e4f">XCsuDma_GetAddr()</a>, <a class="el" href="group__csuma__api.html#ga17f1a7ba935f4bf3626050e0b0e0142b">XCsuDma_GetCheckSum()</a>, <a class="el" href="group__csuma__api.html#gaab0b66bca3f38d26d38ff47544fa6b11">XCsuDma_GetConfig()</a>, <a class="el" href="group__csuma__api.html#ga6ed420e8bfd9ab489a2d2c3e984ca7a2">XCsuDma_GetIntrMask()</a>, <a class="el" href="group__csuma__api.html#gad5fd579fb9c166e59ee1f9d3b39250c7">XCsuDma_GetSize()</a>, <a class="el" href="group__csuma__api.html#ga6169fa380a4d55e41d7ab96589372e8f">XCsuDma_IntrGetStatus()</a>, <a class="el" href="group__csuma__api.html#gaa3450f812658f927f289b997b12a4174">XCsuDma_IsPaused()</a>, <a class="el" href="group__csuma__api.html#ga00b5080126710866186d0bfafd26e9b6">XCsuDma_Pause()</a>, <a class="el" href="group__csuma__api.html#gaeee3f2d5bcf265b57c9f214f2bc15a28">XCsuDma_Resume()</a>, <a class="el" href="group__csuma__api.html#ga774ab551d0ef59fd880ff834f2d83804">XCsuDma_SelfTest()</a>, and <a class="el" href="group__csuma__api.html#gac9b6265e467b03cc903cd66781e95e63">XCsuDma_SetConfig()</a>.</p>

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          <td class="memname">#define XCSUDMA_SIZE_MASK&#160;&#160;&#160;0x1FFFFFFCU</td>
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<p>Mask for size. </p>

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          <td class="memname">#define XCSUDMA_SIZE_OFFSET&#160;&#160;&#160;0x004U</td>
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      </table>
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<p>Size Register Offset. </p>

<p>Referenced by <a class="el" href="group__csuma__api.html#ga83a1043112b6067b1901d2bdcb29563d">XCsuDma_64BitTransfer()</a>, <a class="el" href="group__csuma__api.html#gad5fd579fb9c166e59ee1f9d3b39250c7">XCsuDma_GetSize()</a>, and <a class="el" href="group__csuma__api.html#gacf79144df19e9cd4116dd9f507037ff1">XCsuDma_Transfer()</a>.</p>

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          <td class="memname">#define XCSUDMA_SIZE_SHIFT&#160;&#160;&#160;2U</td>
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<p>Shift for size. </p>

<p>Referenced by <a class="el" href="group__csuma__api.html#ga83a1043112b6067b1901d2bdcb29563d">XCsuDma_64BitTransfer()</a>, <a class="el" href="group__csuma__api.html#gad5fd579fb9c166e59ee1f9d3b39250c7">XCsuDma_GetSize()</a>, and <a class="el" href="group__csuma__api.html#gacf79144df19e9cd4116dd9f507037ff1">XCsuDma_Transfer()</a>.</p>

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          <td class="memname">#define XCSUDMA_STS_OFFSET&#160;&#160;&#160;0x008U</td>
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      </table>
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<p>Status Register Offset. </p>

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          <td class="memname">#define XCSUDMA_WORD_SIZE&#160;&#160;&#160;(4U)</td>
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<p>Transfer size conversion to bytes for Versal Net. </p>

<p>Referenced by <a class="el" href="group__csuma__api.html#ga83a1043112b6067b1901d2bdcb29563d">XCsuDma_64BitTransfer()</a>, and <a class="el" href="group__csuma__api.html#gacf79144df19e9cd4116dd9f507037ff1">XCsuDma_Transfer()</a>.</p>

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          <td class="memname">#define XCsuDma_WriteReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Data&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;<a class="el" href="group__csuma__api.html#gae5b5c8718f050b6b4e25380a92c9aa0d">XCsuDma_Out32</a>((BaseAddress) + (u32)(RegOffset), (u32)(Data))</td>
        </tr>
      </table>
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<p>This macro writes the value into the given register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>Base address of the CSU_DMA core. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>Register offset of the register. </td></tr>
    <tr><td class="paramname">Data</td><td>32-bit value to write to the register.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__csuma__api.html#ga5a2390fe93e02061d01c3b9e057b3b2b" title="This macro writes the value into the given register. ">XCsuDma_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)</a> </dd></dl>

<p>Referenced by <a class="el" href="group__csuma__api.html#ga83a1043112b6067b1901d2bdcb29563d">XCsuDma_64BitTransfer()</a>, <a class="el" href="group__csuma__api.html#ga78bdd79674e2b5c92b9701cacfde1fe1">XCsuDma_ClearCheckSum()</a>, <a class="el" href="group__csuma__api.html#gadf3599e4d07ef05586a217ebbbd02999">XCsuDma_DisableIntr()</a>, <a class="el" href="group__csuma__api.html#gad892a65e65ac14f48f7d7f53020511cf">XCsuDma_EnableIntr()</a>, <a class="el" href="group__csuma__api.html#ga1db5eabd96920efb06fb03c919420601">XCsuDma_IntrClear()</a>, <a class="el" href="group__csuma__api.html#ga00b5080126710866186d0bfafd26e9b6">XCsuDma_Pause()</a>, <a class="el" href="group__csuma__api.html#gaeee3f2d5bcf265b57c9f214f2bc15a28">XCsuDma_Resume()</a>, <a class="el" href="group__csuma__api.html#ga774ab551d0ef59fd880ff834f2d83804">XCsuDma_SelfTest()</a>, <a class="el" href="group__csuma__api.html#gac9b6265e467b03cc903cd66781e95e63">XCsuDma_SetConfig()</a>, and <a class="el" href="group__csuma__api.html#gacf79144df19e9cd4116dd9f507037ff1">XCsuDma_Transfer()</a>.</p>

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<h2 class="groupheader">Enumeration Type Documentation</h2>
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          <td class="memname">enum <a class="el" href="group__csuma__api.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a></td>
        </tr>
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<p>This typedef contains CSU_DMA Channel Types. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><em><a class="anchor" id="gga46008337fdd632f2650b8727c305eba5afe0a7c4c64751afddad37c4a15a00e0d"></a>XCSUDMA_SRC_CHANNEL</em>&nbsp;</td><td class="fielddoc">
<p>Source Channel of CSU_DMA. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="gga46008337fdd632f2650b8727c305eba5a08d300b013b7169bd1475fdf04737fe4"></a>XCSUDMA_DST_CHANNEL</em>&nbsp;</td><td class="fielddoc">
<p>Destination Channel of CSU_DMA. </p>
</td></tr>
</table>

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<h2 class="groupheader">Function Documentation</h2>
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          <td class="memname">void XCsuDma_64BitTransfer </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__csuma__api.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a>&#160;</td>
          <td class="paramname"><em>Channel</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>AddrLow</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>AddrHigh</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Size</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>EnDataLast</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function sets the starting address and size of the data to be transferred from/to the memory through the AXI interface. </p>
<p>This function is useful for pmu processor to execute a 64-bit DMA transfer.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>Pointer to <a class="el" href="struct_x_csu_dma.html" title="The XCsuDma driver instance data structure. ">XCsuDma</a> instance to be worked on. </td></tr>
    <tr><td class="paramname">Channel</td><td>Type of channel Source channel - XCSUDMA_SRC_CHANNEL Destination Channel - XCSUDMA_DST_CHANNEL </td></tr>
    <tr><td class="paramname">AddrLow</td><td>Bit variable which holds the starting lower address of data which needs to write into the memory(DST) (or read from the memory(SRC)). </td></tr>
    <tr><td class="paramname">AddrHigh</td><td>32 bit variable which holds the higher address of data which needs to write into the memory(DST) (or read from the memoroy(SRC)). </td></tr>
    <tr><td class="paramname">Size</td><td>32 bit variable which represents the number of 4 byte words to be transferred from starting address. </td></tr>
    <tr><td class="paramname">EnDataLast</td><td>Trigger an end of message. Enables or disable data_inp_last signal to stream interface when current command is completed. Only applicable for the source channel; ignored for destination channel.<ul>
<li>1 - Asserts data_inp_last signal.</li>
<li>0 - data_inp_last will not be asserted.</li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>Data_inp_last signal is asserted simultaneously with the data_inp_valid signal associated with the final 32-bit word transfer. This API does not invalidate the DMA buffer. It is recommended to call this API only through PMU processor. </dd></dl>

<p>References <a class="el" href="struct_x_csu_dma___config.html#a85e9f7798c5aa5ad4fbc9a8d0ba62990">XCsuDma_Config::BaseAddress</a>, <a class="el" href="struct_x_csu_dma.html#ab64e65f366955cbbc63436336de5ac48">XCsuDma::Config</a>, <a class="el" href="struct_x_csu_dma.html#ab458e2393e0b44a976037f496de9e679">XCsuDma::IsReady</a>, <a class="el" href="group__csuma__api.html#ga76fcd0f2a0c7ebc2058f231a944c7109">XCSUDMA_ADDR_OFFSET</a>, <a class="el" href="group__csuma__api.html#gga46008337fdd632f2650b8727c305eba5a08d300b013b7169bd1475fdf04737fe4">XCSUDMA_DST_CHANNEL</a>, <a class="el" href="group__csuma__api.html#gaf0a5114bb4e675c0e9d933a2d235ac6f">XCSUDMA_LAST_WORD_MASK</a>, <a class="el" href="xcsudma_8h.html#ab57550413ed1c53f70a33ad4b90965eb">XCSUDMA_SIZE_MAX</a>, <a class="el" href="group__csuma__api.html#gaf5d3e01cba7a5d0029901f690007a9c0">XCSUDMA_SIZE_OFFSET</a>, <a class="el" href="group__csuma__api.html#gae1d5689d4fbd05c2e7f6b2a34bcbfb09">XCSUDMA_SIZE_SHIFT</a>, <a class="el" href="group__csuma__api.html#gga46008337fdd632f2650b8727c305eba5afe0a7c4c64751afddad37c4a15a00e0d">XCSUDMA_SRC_CHANNEL</a>, <a class="el" href="group__csuma__api.html#gaf448568bb484f8b80052682f399f194d">XCSUDMA_WORD_SIZE</a>, and <a class="el" href="group__csuma__api.html#ga5a2390fe93e02061d01c3b9e057b3b2b">XCsuDma_WriteReg</a>.</p>

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          <td class="memname">s32 XCsuDma_CfgInitialize </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="struct_x_csu_dma___config.html">XCsuDma_Config</a> *&#160;</td>
          <td class="paramname"><em>CfgPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">UINTPTR&#160;</td>
          <td class="paramname"><em>EffectiveAddr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function initializes CSU_DMA core. </p>
<p>This function must be called prior using a CSU_DMA core. Initialization of an CSU_DMA includes setting up the instance data and ensuring the hardware is in a quiescent state.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>Pointer to the <a class="el" href="struct_x_csu_dma.html" title="The XCsuDma driver instance data structure. ">XCsuDma</a> instance. </td></tr>
    <tr><td class="paramname">CfgPtr</td><td>Reference to a structure containing information about a specific <a class="el" href="struct_x_csu_dma.html" title="The XCsuDma driver instance data structure. ">XCsuDma</a> instance. </td></tr>
    <tr><td class="paramname">EffectiveAddr</td><td>Device base address in the virtual memory address space. The caller is responsible for keeping the address mapping from EffectiveAddr to the device physical base address unchanged once this function is invoked. Unexpected errors may occur if the address mapping changes after this function is called. If address translation is not used, pass in the physical address instead.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if initialization was successful.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_csu_dma___config.html#a85e9f7798c5aa5ad4fbc9a8d0ba62990">XCsuDma_Config::BaseAddress</a>, <a class="el" href="struct_x_csu_dma.html#ab64e65f366955cbbc63436336de5ac48">XCsuDma::Config</a>, <a class="el" href="struct_x_csu_dma___config.html#a8bb59cb926fea92ce59604ca3423e505">XCsuDma_Config::DmaType</a>, <a class="el" href="struct_x_csu_dma.html#ab458e2393e0b44a976037f496de9e679">XCsuDma::IsReady</a>, <a class="el" href="xcsudma_8h.html#a8f5460a8a6a1848b2c4c2988f7428e73">XCSUDMA_DMATYPEIS_CSUDMA</a>, and <a class="el" href="xcsudma_8h.html#a4fd22ed9ee5ff0eae03ee717112b7087">XCsuDma_Reset</a>.</p>

<p>Referenced by <a class="el" href="xcsudma__intr__example_8c.html#ae07b94c3ade7479c4ec8dfec3bb4d643">XCsuDma_IntrExample()</a>, <a class="el" href="xcsudma__polled__example_8c.html#aff327ee48af8d9e5c4018dd4e463674c">XCsuDma_PolledExample()</a>, and <a class="el" href="xcsudma__selftest__example_8c.html#a82ba0686cfea1568bb5a181810625de1">XCsuDma_SelfTestExample()</a>.</p>

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          <td class="memname">void XCsuDma_ClearCheckSum </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
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<p>This function clears the check sum of the data read from AXI memory. </p>
<p>It is valid only for CSU_DMA source channel.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>Pointer to <a class="el" href="struct_x_csu_dma.html" title="The XCsuDma driver instance data structure. ">XCsuDma</a> instance to be worked on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The sum of all the data read from memory.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>Before the transfer starts, clear this register to get correct sum. Otherwise, it adds to previous value which results in an incorrect output. </dd></dl>

<p>References <a class="el" href="struct_x_csu_dma___config.html#a85e9f7798c5aa5ad4fbc9a8d0ba62990">XCsuDma_Config::BaseAddress</a>, <a class="el" href="struct_x_csu_dma.html#ab64e65f366955cbbc63436336de5ac48">XCsuDma::Config</a>, and <a class="el" href="group__csuma__api.html#ga5a2390fe93e02061d01c3b9e057b3b2b">XCsuDma_WriteReg</a>.</p>

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          <td class="memname">void XCsuDma_DisableIntr </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__csuma__api.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a>&#160;</td>
          <td class="paramname"><em>Channel</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Mask</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function disables the interrupt(s). </p>
<p>Use the XCSUDMA_IXR_*_MASK constants defined in <a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a> to create the bit-mask to disable interrupts.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>Pointer to <a class="el" href="struct_x_csu_dma.html" title="The XCsuDma driver instance data structure. ">XCsuDma</a> instance to be worked on. </td></tr>
    <tr><td class="paramname">Channel</td><td>Type of channel Source channel - XCSUDMA_SRC_CHANNEL Destination Channel - XCSUDMA_DST_CHANNEL </td></tr>
    <tr><td class="paramname">Mask</td><td>Contains interrupts to be disabled.<ul>
<li>Bit positions of 1 will be disabled. This mask is formed by OR'ing XCSUDMA_IXR_*_MASK bits defined in <a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>.</li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_csu_dma___config.html#a85e9f7798c5aa5ad4fbc9a8d0ba62990">XCsuDma_Config::BaseAddress</a>, <a class="el" href="struct_x_csu_dma.html#ab64e65f366955cbbc63436336de5ac48">XCsuDma::Config</a>, <a class="el" href="group__csuma__api.html#gga46008337fdd632f2650b8727c305eba5a08d300b013b7169bd1475fdf04737fe4">XCSUDMA_DST_CHANNEL</a>, <a class="el" href="group__csuma__api.html#gadfb7ef2922c9ceb4804bc87620c35134">XCSUDMA_IXR_DST_MASK</a>, <a class="el" href="group__csuma__api.html#ga441edc2ec9eadb8093ac0ab41e0162d2">XCSUDMA_IXR_SRC_MASK</a>, <a class="el" href="group__csuma__api.html#gga46008337fdd632f2650b8727c305eba5afe0a7c4c64751afddad37c4a15a00e0d">XCSUDMA_SRC_CHANNEL</a>, and <a class="el" href="group__csuma__api.html#ga5a2390fe93e02061d01c3b9e057b3b2b">XCsuDma_WriteReg</a>.</p>

<p>Referenced by <a class="el" href="xcsudma__intr__example_8c.html#ae07b94c3ade7479c4ec8dfec3bb4d643">XCsuDma_IntrExample()</a>.</p>

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          <td class="memname">void XCsuDma_EnableIntr </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__csuma__api.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a>&#160;</td>
          <td class="paramname"><em>Channel</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Mask</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function enables the interrupt(s). </p>
<p>Use the XCSUDMA_IXR_*_MASK constants defined in <a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a> to create the bit-mask to enable interrupts.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>Pointer to <a class="el" href="struct_x_csu_dma.html" title="The XCsuDma driver instance data structure. ">XCsuDma</a> instance to be worked on. </td></tr>
    <tr><td class="paramname">Channel</td><td>Type of channel Source channel - XCSUDMA_SRC_CHANNEL Destination Channel - XCSUDMA_DST_CHANNEL </td></tr>
    <tr><td class="paramname">Mask</td><td>Contains interrupts to be enabled.<ul>
<li>Bit positions of 1 will be enabled. This mask is formed by OR'ing XCSUDMA_IXR_*_MASK bits defined in <a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>.</li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_csu_dma___config.html#a85e9f7798c5aa5ad4fbc9a8d0ba62990">XCsuDma_Config::BaseAddress</a>, <a class="el" href="struct_x_csu_dma.html#ab64e65f366955cbbc63436336de5ac48">XCsuDma::Config</a>, <a class="el" href="group__csuma__api.html#gga46008337fdd632f2650b8727c305eba5a08d300b013b7169bd1475fdf04737fe4">XCSUDMA_DST_CHANNEL</a>, <a class="el" href="group__csuma__api.html#gadfb7ef2922c9ceb4804bc87620c35134">XCSUDMA_IXR_DST_MASK</a>, <a class="el" href="group__csuma__api.html#ga441edc2ec9eadb8093ac0ab41e0162d2">XCSUDMA_IXR_SRC_MASK</a>, <a class="el" href="group__csuma__api.html#gga46008337fdd632f2650b8727c305eba5afe0a7c4c64751afddad37c4a15a00e0d">XCSUDMA_SRC_CHANNEL</a>, and <a class="el" href="group__csuma__api.html#ga5a2390fe93e02061d01c3b9e057b3b2b">XCsuDma_WriteReg</a>.</p>

<p>Referenced by <a class="el" href="xcsudma__intr__example_8c.html#ae07b94c3ade7479c4ec8dfec3bb4d643">XCsuDma_IntrExample()</a>.</p>

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          <td class="memname">u64 XCsuDma_GetAddr </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__csuma__api.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a>&#160;</td>
          <td class="paramname"><em>Channel</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function returns the current address location of the memory, from where it has to read the data(SRC) or the location where it has to write the data (DST) based on the channel selection. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>Pointer to <a class="el" href="struct_x_csu_dma.html" title="The XCsuDma driver instance data structure. ">XCsuDma</a> instance to be worked on. </td></tr>
    <tr><td class="paramname">Channel</td><td>Type of channel Source channel - XCSUDMA_SRC_CHANNEL Destination Channel - XCSUDMA_DST_CHANNEL</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Address is a 64 bit variable which holds the current address.<ul>
<li>From this location data has to be read(SRC)</li>
<li>At this location data has to be written(DST)</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_csu_dma___config.html#a85e9f7798c5aa5ad4fbc9a8d0ba62990">XCsuDma_Config::BaseAddress</a>, <a class="el" href="struct_x_csu_dma.html#ab64e65f366955cbbc63436336de5ac48">XCsuDma::Config</a>, <a class="el" href="group__csuma__api.html#ga76fcd0f2a0c7ebc2058f231a944c7109">XCSUDMA_ADDR_OFFSET</a>, <a class="el" href="group__csuma__api.html#gga46008337fdd632f2650b8727c305eba5a08d300b013b7169bd1475fdf04737fe4">XCSUDMA_DST_CHANNEL</a>, <a class="el" href="group__csuma__api.html#ga356d29aa2d43a1b724700007be7dcd51">XCsuDma_ReadReg</a>, and <a class="el" href="group__csuma__api.html#gga46008337fdd632f2650b8727c305eba5afe0a7c4c64751afddad37c4a15a00e0d">XCSUDMA_SRC_CHANNEL</a>.</p>

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          <td class="memname">u32 XCsuDma_GetCheckSum </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
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<p>This function returns the sum of all the data read from AXI memory. </p>
<p>It is valid only when using the CSU_DMA source channel.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>Pointer to <a class="el" href="struct_x_csu_dma.html" title="The XCsuDma driver instance data structure. ">XCsuDma</a> instance to be worked on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The sum of all the data read from memory.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>Before the transfer starts, clear this register to get the correct sum. Otherwise, it adds to previous value which results in an incorrect output. Valid only for source channel. </dd></dl>

<p>References <a class="el" href="struct_x_csu_dma___config.html#a85e9f7798c5aa5ad4fbc9a8d0ba62990">XCsuDma_Config::BaseAddress</a>, <a class="el" href="struct_x_csu_dma.html#ab64e65f366955cbbc63436336de5ac48">XCsuDma::Config</a>, <a class="el" href="struct_x_csu_dma.html#ab458e2393e0b44a976037f496de9e679">XCsuDma::IsReady</a>, and <a class="el" href="group__csuma__api.html#ga356d29aa2d43a1b724700007be7dcd51">XCsuDma_ReadReg</a>.</p>

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          <td class="memname">void XCsuDma_GetConfig </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__csuma__api.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a>&#160;</td>
          <td class="paramname"><em>Channel</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="struct_x_csu_dma___configure.html">XCsuDma_Configure</a> *&#160;</td>
          <td class="paramname"><em>ConfigurValues</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function updates <a class="el" href="struct_x_csu_dma___configure.html" title="This typedef contains all the configuration feilds which must be set before the start of the data tra...">XCsuDma_Configure</a> structure members with the configured values of CSU_DMA's Channel. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>Pointer to <a class="el" href="struct_x_csu_dma.html" title="The XCsuDma driver instance data structure. ">XCsuDma</a> instance to be worked on. </td></tr>
    <tr><td class="paramname">Channel</td><td>Type of channel Source channel - XCSUDMA_SRC_CHANNEL Destination Channel - XCSUDMA_DST_CHANNEL </td></tr>
    <tr><td class="paramname">ConfigurValues</td><td>Pointer to the structure <a class="el" href="struct_x_csu_dma___configure.html" title="This typedef contains all the configuration feilds which must be set before the start of the data tra...">XCsuDma_Configure</a> whose members are updated with configurations of CSU_DMA core.<ul>
<li>SssFifoThesh: When the DST FIFO level &gt;= this value, the SSS interface signal, "data_out_fifo_level_hit" will be asserted. This mechanism can be used by the SSS to flow control data that is being looped back from the SRC DMA.<ul>
<li>Range is (0x10 to 0x7A) threshold is 17 to 123 entries.</li>
<li>It is valid only for DST CSU_DMA IP.</li>
</ul>
</li>
<li>ApbErr: When accessed to invalid APB the resulting pslerr will be<ul>
<li>0 - 1'b0</li>
<li>1 - 1'b1</li>
</ul>
</li>
<li>EndianType: Type of endianness<ul>
<li>0 doesn't change order</li>
<li>1 will flip the order.</li>
</ul>
</li>
<li>AxiBurstType: Type of the burst<ul>
<li>0 will issue INCR type burst</li>
<li>1 will issue FIXED type burst</li>
</ul>
</li>
<li>TimeoutValue: Time out value for timers<ul>
<li>0x000 to 0xFFE are valid inputs</li>
<li>0xFFF clears both timers</li>
</ul>
</li>
<li>FifoThresh: Programmed watermark value<ul>
<li>Range is 0x00 to 0x80 (0 to 128 entries).</li>
</ul>
</li>
<li>Acache: Sets the AXI CACHE bits on the AXI Write/Read channel.<ul>
<li>Cacheable ARCACHE[1] for SRC Channel and AWCACHE[1] for DST channel are always 1, we need to configure remaining 3 signal support (Bufferable, Read allocate and Write allocate). Valid inputs are:</li>
<li>0x000 - Cacheable, but do not allocate</li>
<li>0x001 - Cacheable and bufferable, but do not allocate</li>
<li>0x010 - Cacheable write-through, allocate on reads only</li>
<li>0x011 - Cacheable write-back, allocate on reads only</li>
<li>0x100 - Cacheable write-through, allocate on writes only</li>
<li>0x101 - Cacheable write-back, allocate on writes only</li>
<li>0x110 - Cacheable write-through, allocate on both reads and writes</li>
<li>0x111 - Cacheable write-back, allocate on both reads and writes</li>
</ul>
</li>
<li>RouteBit: To select route<ul>
<li>0 : Command will be routed based normally</li>
<li>1 : Command will be routed to APU's cache controller</li>
</ul>
</li>
<li>TimeoutEn: To enable or disable time out counters<ul>
<li>0 : The 2 Timeout counters are disabled</li>
<li>1 : The 2 Timeout counters are enabled</li>
</ul>
</li>
<li>TimeoutPre: Set the prescaler value for the timeout in clk (~2.5ns) cycles<ul>
<li>Range is 0x000(Prescaler enables timer every cycles) to 0xFFF(Prescaler enables timer every 4096 cycles)</li>
</ul>
</li>
<li>MaxOutCmds: Controls the maximumum number of outstanding AXI read commands issued.<ul>
<li>Range is 0x0(Up to 1 Outstanding Read command allowed) to 0x8 (Up to 9 Outstanding Read command allowed)</li>
</ul>
</li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_csu_dma___configure.html#a984f69d8fa925618e85800ba8fd2d155">XCsuDma_Configure::Acache</a>, <a class="el" href="struct_x_csu_dma___configure.html#a7ca88dbe204c7b24ce7e529da53e1ae2">XCsuDma_Configure::ApbErr</a>, <a class="el" href="struct_x_csu_dma___configure.html#a1aeadd99f4f96da636b9cb0c2be21c09">XCsuDma_Configure::AxiBurstType</a>, <a class="el" href="struct_x_csu_dma___config.html#a85e9f7798c5aa5ad4fbc9a8d0ba62990">XCsuDma_Config::BaseAddress</a>, <a class="el" href="struct_x_csu_dma.html#ab64e65f366955cbbc63436336de5ac48">XCsuDma::Config</a>, <a class="el" href="struct_x_csu_dma___configure.html#a4d1217d471a558f54534c15213bbb264">XCsuDma_Configure::EndianType</a>, <a class="el" href="struct_x_csu_dma___configure.html#af17af84045f926ff8e386509cc0c9aee">XCsuDma_Configure::FifoThresh</a>, <a class="el" href="struct_x_csu_dma___configure.html#acdf6a30da74f891648e17d1ce9bfadae">XCsuDma_Configure::MaxOutCmds</a>, <a class="el" href="struct_x_csu_dma___configure.html#ac6f8c811d5b1ecf86d37091fc132717e">XCsuDma_Configure::RouteBit</a>, <a class="el" href="struct_x_csu_dma___configure.html#a524260e03c75bc8745da0e4b7dca71ed">XCsuDma_Configure::SssFifoThesh</a>, <a class="el" href="struct_x_csu_dma___configure.html#a2f45ba702e0487ed32152186339d7052">XCsuDma_Configure::TimeoutEn</a>, <a class="el" href="struct_x_csu_dma___configure.html#a00365f4d0973fcb3fd39382312775748">XCsuDma_Configure::TimeoutPre</a>, <a class="el" href="struct_x_csu_dma___configure.html#af2b9f211561ad313b726a60104afc32e">XCsuDma_Configure::TimeoutValue</a>, <a class="el" href="group__csuma__api.html#ga60d1ed5209af6a5d9e9c55b6b95052de">XCSUDMA_CTRL_OFFSET</a>, <a class="el" href="group__csuma__api.html#gga46008337fdd632f2650b8727c305eba5a08d300b013b7169bd1475fdf04737fe4">XCSUDMA_DST_CHANNEL</a>, <a class="el" href="group__csuma__api.html#ga356d29aa2d43a1b724700007be7dcd51">XCsuDma_ReadReg</a>, and <a class="el" href="group__csuma__api.html#gga46008337fdd632f2650b8727c305eba5afe0a7c4c64751afddad37c4a15a00e0d">XCSUDMA_SRC_CHANNEL</a>.</p>

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          <td class="memname">u32 XCsuDma_GetIntrMask </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__csuma__api.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a>&#160;</td>
          <td class="paramname"><em>Channel</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function returns the interrupt mask to know which interrupts are enabled and which of them were disaled. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>Pointer to <a class="el" href="struct_x_csu_dma.html" title="The XCsuDma driver instance data structure. ">XCsuDma</a> instance to be worked on. </td></tr>
    <tr><td class="paramname">Channel</td><td>Type of channel Source channel - XCSUDMA_SRC_CHANNEL Destination Channel - XCSUDMA_DST_CHANNEL</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The current interrupt mask. The mask indicates which interrupts are enabled/disabled.<ul>
<li>0 bit represents that the corresponding interrupt is enabled.</li>
<li>1 bit represents that the Corresponding interrupt is disabled. To interpret returned mask use</li>
<li>XCSUDMA_IXR_SRC_MASK that the For source channel</li>
<li>XCSUDMA_IXR_DST_MASK that the For destination channel</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_csu_dma___config.html#a85e9f7798c5aa5ad4fbc9a8d0ba62990">XCsuDma_Config::BaseAddress</a>, <a class="el" href="struct_x_csu_dma.html#ab64e65f366955cbbc63436336de5ac48">XCsuDma::Config</a>, <a class="el" href="group__csuma__api.html#gga46008337fdd632f2650b8727c305eba5a08d300b013b7169bd1475fdf04737fe4">XCSUDMA_DST_CHANNEL</a>, <a class="el" href="group__csuma__api.html#ga356d29aa2d43a1b724700007be7dcd51">XCsuDma_ReadReg</a>, and <a class="el" href="group__csuma__api.html#gga46008337fdd632f2650b8727c305eba5afe0a7c4c64751afddad37c4a15a00e0d">XCSUDMA_SRC_CHANNEL</a>.</p>

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          <td class="memname">u32 XCsuDma_GetSize </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__csuma__api.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a>&#160;</td>
          <td class="paramname"><em>Channel</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This function returns the size of the data yet to be transferred from memory to CSU_DMA or CSU_DMA to memory based on the channel selection. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>Pointer to <a class="el" href="struct_x_csu_dma.html" title="The XCsuDma driver instance data structure. ">XCsuDma</a> instance to be worked on. </td></tr>
    <tr><td class="paramname">Channel</td><td>Type of channel Source channel - XCSUDMA_SRC_CHANNEL Destination Channel - XCSUDMA_DST_CHANNEL</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Returns number of bytes of data yet to be transferred.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_csu_dma___config.html#a85e9f7798c5aa5ad4fbc9a8d0ba62990">XCsuDma_Config::BaseAddress</a>, <a class="el" href="struct_x_csu_dma.html#ab64e65f366955cbbc63436336de5ac48">XCsuDma::Config</a>, <a class="el" href="group__csuma__api.html#gga46008337fdd632f2650b8727c305eba5a08d300b013b7169bd1475fdf04737fe4">XCSUDMA_DST_CHANNEL</a>, <a class="el" href="group__csuma__api.html#ga356d29aa2d43a1b724700007be7dcd51">XCsuDma_ReadReg</a>, <a class="el" href="group__csuma__api.html#gaf5d3e01cba7a5d0029901f690007a9c0">XCSUDMA_SIZE_OFFSET</a>, <a class="el" href="group__csuma__api.html#gae1d5689d4fbd05c2e7f6b2a34bcbfb09">XCSUDMA_SIZE_SHIFT</a>, and <a class="el" href="group__csuma__api.html#gga46008337fdd632f2650b8727c305eba5afe0a7c4c64751afddad37c4a15a00e0d">XCSUDMA_SRC_CHANNEL</a>.</p>

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          <td class="memname">void XCsuDma_IntrClear </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__csuma__api.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a>&#160;</td>
          <td class="paramname"><em>Channel</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Mask</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
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<p>This function clears interrupt(s). </p>
<p>Every bit set in Interrupt Status Register indicates that a specific type of interrupt is occurring, and this function clears one or more interrupts by writing a bit mask to Interrupt Clear Register.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>Pointer to <a class="el" href="struct_x_csu_dma.html" title="The XCsuDma driver instance data structure. ">XCsuDma</a> instance to be worked on. </td></tr>
    <tr><td class="paramname">Channel</td><td>Type of channel Source channel - XCSUDMA_SRC_CHANNEL Destination Channel - XCSUDMA_DST_CHANNEL </td></tr>
    <tr><td class="paramname">Mask</td><td>Mask to clear. Bit positions of 1 will be cleared. Bit positions of 0 will not change the previous interrupt status. This mask is formed by OR'ing XCSUDMA_IXR_* bits defined in <a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a>.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_csu_dma___config.html#a85e9f7798c5aa5ad4fbc9a8d0ba62990">XCsuDma_Config::BaseAddress</a>, <a class="el" href="struct_x_csu_dma.html#ab64e65f366955cbbc63436336de5ac48">XCsuDma::Config</a>, <a class="el" href="group__csuma__api.html#gga46008337fdd632f2650b8727c305eba5a08d300b013b7169bd1475fdf04737fe4">XCSUDMA_DST_CHANNEL</a>, <a class="el" href="group__csuma__api.html#gab56adb100901bb2b042a842619064ce5">XCSUDMA_I_STS_OFFSET</a>, <a class="el" href="group__csuma__api.html#gadfb7ef2922c9ceb4804bc87620c35134">XCSUDMA_IXR_DST_MASK</a>, <a class="el" href="group__csuma__api.html#ga441edc2ec9eadb8093ac0ab41e0162d2">XCSUDMA_IXR_SRC_MASK</a>, <a class="el" href="group__csuma__api.html#gga46008337fdd632f2650b8727c305eba5afe0a7c4c64751afddad37c4a15a00e0d">XCSUDMA_SRC_CHANNEL</a>, and <a class="el" href="group__csuma__api.html#ga5a2390fe93e02061d01c3b9e057b3b2b">XCsuDma_WriteReg</a>.</p>

<p>Referenced by <a class="el" href="xcsudma__intr__example_8c.html#ae07b94c3ade7479c4ec8dfec3bb4d643">XCsuDma_IntrExample()</a>, and <a class="el" href="xcsudma__polled__example_8c.html#aff327ee48af8d9e5c4018dd4e463674c">XCsuDma_PolledExample()</a>.</p>

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          <td class="memname">u32 XCsuDma_IntrGetStatus </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__csuma__api.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a>&#160;</td>
          <td class="paramname"><em>Channel</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function returns interrupt status read from Interrupt Status Register. </p>
<p>Use the XCSUDMA_IXR_*_MASK constants defined in <a class="el" href="xcsudma__hw_8h.html">xcsudma_hw.h</a> to interpret the returned value.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>Pointer to <a class="el" href="struct_x_csu_dma.html" title="The XCsuDma driver instance data structure. ">XCsuDma</a> instance to be worked on. </td></tr>
    <tr><td class="paramname">Channel</td><td>Type of channel Source channel - XCSUDMA_SRC_CHANNEL Destination Channel - XCSUDMA_DST_CHANNEL</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The pending interrupts of the CSU_DMA. Use th following masks to interpret the returned value. XCSUDMA_IXR_SRC_MASK - For Source channel XCSUDMA_IXR_DST_MASK - For Destination channel</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_csu_dma___config.html#a85e9f7798c5aa5ad4fbc9a8d0ba62990">XCsuDma_Config::BaseAddress</a>, <a class="el" href="struct_x_csu_dma.html#ab64e65f366955cbbc63436336de5ac48">XCsuDma::Config</a>, <a class="el" href="group__csuma__api.html#gga46008337fdd632f2650b8727c305eba5a08d300b013b7169bd1475fdf04737fe4">XCSUDMA_DST_CHANNEL</a>, <a class="el" href="group__csuma__api.html#gab56adb100901bb2b042a842619064ce5">XCSUDMA_I_STS_OFFSET</a>, <a class="el" href="group__csuma__api.html#ga356d29aa2d43a1b724700007be7dcd51">XCsuDma_ReadReg</a>, and <a class="el" href="group__csuma__api.html#gga46008337fdd632f2650b8727c305eba5afe0a7c4c64751afddad37c4a15a00e0d">XCSUDMA_SRC_CHANNEL</a>.</p>

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          <td class="memname">s32 XCsuDma_IsPaused </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__csuma__api.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a>&#160;</td>
          <td class="paramname"><em>Channel</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="xcsudma_8h.html#ad5ce08d197288cbdfb06941f1d46df87">XCsuDma_PauseType</a>&#160;</td>
          <td class="paramname"><em>Type</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
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<p>This function checks whether Channel memory/stream is paused based on the given pause type. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>Pointer to <a class="el" href="struct_x_csu_dma.html" title="The XCsuDma driver instance data structure. ">XCsuDma</a> instance to be worked on. </td></tr>
    <tr><td class="paramname">Channel</td><td>Type of channel Source channel - XCSUDMA_SRC_CHANNEL Destination Channel - XCSUDMA_DST_CHANNEL </td></tr>
    <tr><td class="paramname">Type</td><td>Type of the pause which needs to be checked.<ul>
<li>XCSUDMA_PAUSE_MEMORY(0) - Pause memory<ul>
<li>SRC stops issuing new read commands to memory.</li>
<li>DST stops issuing new write commands to memory.</li>
</ul>
</li>
<li>XCSUDMA_PAUSE_STREAM(1) - Pause stream<ul>
<li>SRC stops the transfer of data from FIFO to Stream.</li>
<li>DST stops the transfer of data from stream to FIFO.</li>
</ul>
</li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Returns the pause status.<ul>
<li>TRUE if it is in paused state.</li>
<li>FALSE if it is not in pause state.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_csu_dma___config.html#a85e9f7798c5aa5ad4fbc9a8d0ba62990">XCsuDma_Config::BaseAddress</a>, <a class="el" href="struct_x_csu_dma.html#ab64e65f366955cbbc63436336de5ac48">XCsuDma::Config</a>, <a class="el" href="group__csuma__api.html#ga60d1ed5209af6a5d9e9c55b6b95052de">XCSUDMA_CTRL_OFFSET</a>, <a class="el" href="group__csuma__api.html#gga46008337fdd632f2650b8727c305eba5a08d300b013b7169bd1475fdf04737fe4">XCSUDMA_DST_CHANNEL</a>, <a class="el" href="xcsudma_8h.html#ad5ce08d197288cbdfb06941f1d46df87a4848b0d503f02b0b03be6cd1a14ef6a8">XCSUDMA_PAUSE_MEMORY</a>, <a class="el" href="xcsudma_8h.html#ad5ce08d197288cbdfb06941f1d46df87a67086fbe749ed37f5928c211ee6aa5b8">XCSUDMA_PAUSE_STREAM</a>, <a class="el" href="group__csuma__api.html#ga356d29aa2d43a1b724700007be7dcd51">XCsuDma_ReadReg</a>, and <a class="el" href="group__csuma__api.html#gga46008337fdd632f2650b8727c305eba5afe0a7c4c64751afddad37c4a15a00e0d">XCSUDMA_SRC_CHANNEL</a>.</p>

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          <td class="memname"><a class="el" href="struct_x_csu_dma___config.html">XCsuDma_Config</a>* XCsuDma_LookupConfig </td>
          <td>(</td>
          <td class="paramtype">u16&#160;</td>
          <td class="paramname"><em>DeviceId</em></td><td>)</td>
          <td></td>
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<p>XCsuDma_LookupConfig returns a reference to an <a class="el" href="struct_x_csu_dma___config.html" title="This typedef contains configuration information for a CSU_DMA core. ">XCsuDma_Config</a> structure based on the unique device id, <em>DeviceId</em>. </p>
<p>The return value will refer to an entry in the device configuration table defined in the xcsudma_g.c file.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">DeviceId</td><td>Unique device ID of the device for the lookup operation.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>CfgPtr is a reference to a config record in the configuration table (in xcsudma_g.c) corresponding to <em>DeviceId</em>, or NULL if no match is found.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>Referenced by <a class="el" href="xcsudma__intr__example_8c.html#ae07b94c3ade7479c4ec8dfec3bb4d643">XCsuDma_IntrExample()</a>, <a class="el" href="xcsudma__polled__example_8c.html#aff327ee48af8d9e5c4018dd4e463674c">XCsuDma_PolledExample()</a>, and <a class="el" href="xcsudma__selftest__example_8c.html#a82ba0686cfea1568bb5a181810625de1">XCsuDma_SelfTestExample()</a>.</p>

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          <td class="memname">void XCsuDma_Pause </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__csuma__api.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a>&#160;</td>
          <td class="paramname"><em>Channel</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="xcsudma_8h.html#ad5ce08d197288cbdfb06941f1d46df87">XCsuDma_PauseType</a>&#160;</td>
          <td class="paramname"><em>Type</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This function pauses the Channel data transfer to/from memory or to/from stream based on pause type. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>Pointer to <a class="el" href="struct_x_csu_dma.html" title="The XCsuDma driver instance data structure. ">XCsuDma</a> instance to be worked on. </td></tr>
    <tr><td class="paramname">Channel</td><td>Type of channel Source channel - XCSUDMA_SRC_CHANNEL Destination Channel - XCSUDMA_DST_CHANNEL </td></tr>
    <tr><td class="paramname">Type</td><td>Type of pause to be enabled.<ul>
<li>XCSUDMA_PAUSE_MEMORY(0) - Pause memory<ul>
<li>SRC stops issuing new read commands to memory.</li>
<li>DST stops issuing new write commands to memory.</li>
</ul>
</li>
<li>XCSUDMA_PAUSE_STREAM(1) - Pause stream<ul>
<li>SRC stops the transfer of data from FIFO to Stream.</li>
<li>DST stops the transfer of data from stream to FIFO.</li>
</ul>
</li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_csu_dma___config.html#a85e9f7798c5aa5ad4fbc9a8d0ba62990">XCsuDma_Config::BaseAddress</a>, <a class="el" href="struct_x_csu_dma.html#ab64e65f366955cbbc63436336de5ac48">XCsuDma::Config</a>, <a class="el" href="struct_x_csu_dma.html#ab458e2393e0b44a976037f496de9e679">XCsuDma::IsReady</a>, <a class="el" href="group__csuma__api.html#ga60d1ed5209af6a5d9e9c55b6b95052de">XCSUDMA_CTRL_OFFSET</a>, <a class="el" href="group__csuma__api.html#gga46008337fdd632f2650b8727c305eba5a08d300b013b7169bd1475fdf04737fe4">XCSUDMA_DST_CHANNEL</a>, <a class="el" href="xcsudma_8h.html#ad5ce08d197288cbdfb06941f1d46df87a4848b0d503f02b0b03be6cd1a14ef6a8">XCSUDMA_PAUSE_MEMORY</a>, <a class="el" href="xcsudma_8h.html#ad5ce08d197288cbdfb06941f1d46df87a67086fbe749ed37f5928c211ee6aa5b8">XCSUDMA_PAUSE_STREAM</a>, <a class="el" href="group__csuma__api.html#ga356d29aa2d43a1b724700007be7dcd51">XCsuDma_ReadReg</a>, <a class="el" href="group__csuma__api.html#gga46008337fdd632f2650b8727c305eba5afe0a7c4c64751afddad37c4a15a00e0d">XCSUDMA_SRC_CHANNEL</a>, and <a class="el" href="group__csuma__api.html#ga5a2390fe93e02061d01c3b9e057b3b2b">XCsuDma_WriteReg</a>.</p>

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          <td class="memname">void XCsuDma_Resume </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__csuma__api.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a>&#160;</td>
          <td class="paramname"><em>Channel</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="xcsudma_8h.html#ad5ce08d197288cbdfb06941f1d46df87">XCsuDma_PauseType</a>&#160;</td>
          <td class="paramname"><em>Type</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This function resumes the channel if it is in paused state and continues where it has left. </p>
<p>Based on the type of pause, there is no effect if it is not in paused state.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>Pointer to <a class="el" href="struct_x_csu_dma.html" title="The XCsuDma driver instance data structure. ">XCsuDma</a> instance to be worked on. </td></tr>
    <tr><td class="paramname">Channel</td><td>Type of channel Source channel - XCSUDMA_SRC_CHANNEL Destination Channel - XCSUDMA_DST_CHANNEL </td></tr>
    <tr><td class="paramname">Type</td><td>Type of pause to be resumed if it is paused.<ul>
<li>XCSUDMA_PAUSE_MEMORY(0) - Pause memory<ul>
<li>SRC stops issuing new read commands to memory.</li>
<li>DST stops issuing new write commands to memory.</li>
</ul>
</li>
<li>XCSUDMA_PAUSE_STREAM(1) - Pause stream<ul>
<li>SRC stops the transfer of data from FIFO to Stream.</li>
<li>DST stops the transfer of data from stream to FIFO.</li>
</ul>
</li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_csu_dma___config.html#a85e9f7798c5aa5ad4fbc9a8d0ba62990">XCsuDma_Config::BaseAddress</a>, <a class="el" href="struct_x_csu_dma.html#ab64e65f366955cbbc63436336de5ac48">XCsuDma::Config</a>, <a class="el" href="struct_x_csu_dma.html#ab458e2393e0b44a976037f496de9e679">XCsuDma::IsReady</a>, <a class="el" href="group__csuma__api.html#ga60d1ed5209af6a5d9e9c55b6b95052de">XCSUDMA_CTRL_OFFSET</a>, <a class="el" href="group__csuma__api.html#gga46008337fdd632f2650b8727c305eba5a08d300b013b7169bd1475fdf04737fe4">XCSUDMA_DST_CHANNEL</a>, <a class="el" href="xcsudma_8h.html#ad5ce08d197288cbdfb06941f1d46df87a4848b0d503f02b0b03be6cd1a14ef6a8">XCSUDMA_PAUSE_MEMORY</a>, <a class="el" href="xcsudma_8h.html#ad5ce08d197288cbdfb06941f1d46df87a67086fbe749ed37f5928c211ee6aa5b8">XCSUDMA_PAUSE_STREAM</a>, <a class="el" href="group__csuma__api.html#ga356d29aa2d43a1b724700007be7dcd51">XCsuDma_ReadReg</a>, <a class="el" href="group__csuma__api.html#gga46008337fdd632f2650b8727c305eba5afe0a7c4c64751afddad37c4a15a00e0d">XCSUDMA_SRC_CHANNEL</a>, and <a class="el" href="group__csuma__api.html#ga5a2390fe93e02061d01c3b9e057b3b2b">XCsuDma_WriteReg</a>.</p>

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          <td class="memname">s32 XCsuDma_SelfTest </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
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<p>This function runs a self-test on the driver and hardware device. </p>
<p>Performs reset of both source and destination channels and checks if reset is working properly or not.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>Pointer to the <a class="el" href="struct_x_csu_dma.html" title="The XCsuDma driver instance data structure. ">XCsuDma</a> instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if the self-test passed.<ul>
<li>XST_FAILURE otherwise.</li>
</ul>
</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_csu_dma___config.html#a85e9f7798c5aa5ad4fbc9a8d0ba62990">XCsuDma_Config::BaseAddress</a>, <a class="el" href="struct_x_csu_dma.html#ab64e65f366955cbbc63436336de5ac48">XCsuDma::Config</a>, <a class="el" href="group__csuma__api.html#ga60d1ed5209af6a5d9e9c55b6b95052de">XCSUDMA_CTRL_OFFSET</a>, <a class="el" href="group__csuma__api.html#ga356d29aa2d43a1b724700007be7dcd51">XCsuDma_ReadReg</a>, and <a class="el" href="group__csuma__api.html#ga5a2390fe93e02061d01c3b9e057b3b2b">XCsuDma_WriteReg</a>.</p>

<p>Referenced by <a class="el" href="xcsudma__intr__example_8c.html#ae07b94c3ade7479c4ec8dfec3bb4d643">XCsuDma_IntrExample()</a>, <a class="el" href="xcsudma__polled__example_8c.html#aff327ee48af8d9e5c4018dd4e463674c">XCsuDma_PolledExample()</a>, and <a class="el" href="xcsudma__selftest__example_8c.html#a82ba0686cfea1568bb5a181810625de1">XCsuDma_SelfTestExample()</a>.</p>

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          <td class="memname">void XCsuDma_SetConfig </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__csuma__api.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a>&#160;</td>
          <td class="paramname"><em>Channel</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="struct_x_csu_dma___configure.html">XCsuDma_Configure</a> *&#160;</td>
          <td class="paramname"><em>ConfigurValues</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function configures all the values of CSU_DMA Channels with the values of updated <a class="el" href="struct_x_csu_dma___configure.html" title="This typedef contains all the configuration feilds which must be set before the start of the data tra...">XCsuDma_Configure</a> structure. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>Pointer to <a class="el" href="struct_x_csu_dma.html" title="The XCsuDma driver instance data structure. ">XCsuDma</a> instance to be worked on. </td></tr>
    <tr><td class="paramname">Channel</td><td>Type of channel Source channel - XCSUDMA_SRC_CHANNEL Destination Channel - XCSUDMA_DST_CHANNEL </td></tr>
    <tr><td class="paramname">ConfigurValues</td><td>Pointer to the structure <a class="el" href="struct_x_csu_dma___configure.html" title="This typedef contains all the configuration feilds which must be set before the start of the data tra...">XCsuDma_Configure</a> whose values are used to configure CSU_DMA core.<ul>
<li>SssFifoThesh: When the DST FIFO level &gt;= this value, the SSS interface signal, "data_out_fifo_level_hit" is asserted. This mechanism can be used by the SSS to flow control data that is being looped back from the SRC DMA.<ul>
<li>Range is (0x10 to 0x7A) threshold is 17 to 123 entries.</li>
<li>It is valid only for DST CSU_DMA IP.</li>
</ul>
</li>
<li>ApbErr: When accessed to invalid APB the resulting pslerr will be<ul>
<li>0 - 1'b0</li>
<li>1 - 1'b1</li>
</ul>
</li>
<li>EndianType: Type of endianness<ul>
<li>0 doesn't change order</li>
<li>1 will flip the order.</li>
</ul>
</li>
<li>AxiBurstType: Type of the burst<ul>
<li>0 will issue INCR type burst</li>
<li>1 will issue FIXED type burst</li>
</ul>
</li>
<li>TimeoutValue: Time out value for timers<ul>
<li>0x000 to 0xFFE are valid inputs</li>
<li>0xFFF clears both timers</li>
</ul>
</li>
<li>FifoThresh: Programmed watermark value<ul>
<li>Range is 0x00 to 0x80 (0 to 128 entries).</li>
</ul>
</li>
<li>Acache: Sets the AXI CACHE bits on the AXI Write/Read channel.<ul>
<li>Cacheable ARCACHE[1] for SRC Channel and AWCACHE[1] for DST channel are always 1, we need to configure remaining 3 signal support (Bufferable, Read allocate and Write allocate). Valid inputs are:</li>
<li>0x000 - Cacheable, but do not allocate</li>
<li>0x001 - Cacheable and bufferable, but do not allocate</li>
<li>0x010 - Cacheable write-through, allocate on reads only</li>
<li>0x011 - Cacheable write-back, allocate on reads only</li>
<li>0x100 - Cacheable write-through, allocate on writes only</li>
<li>0x101 - Cacheable write-back, allocate on writes only</li>
<li>0x110 - Cacheable write-through, allocate on both reads and writes</li>
<li>0x111 - Cacheable write-back, allocate on both reads and writes</li>
</ul>
</li>
<li>RouteBit: To select route<ul>
<li>0 : Command will be routed normally</li>
<li>1 : Command will be routed to APU's cache controller</li>
</ul>
</li>
<li>TimeoutEn: To enable or disable time out counters<ul>
<li>0 : The 2 Timeout counters are disabled</li>
<li>1 : The 2 Timeout counters are enabled</li>
</ul>
</li>
<li>TimeoutPre: Set the prescaler value for the timeout in clk (~2.5ns) cycles<ul>
<li>Range is 0x000(Prescaler enables timer every cycles) to 0xFFF(Prescaler enables timer every 4096 cycles)</li>
</ul>
</li>
<li>MaxOutCmds: Controls the maximumum number of outstanding AXI read commands issued.<ul>
<li>Range is 0x0(Up to 1 Outstanding Read command allowed) to 0x8 (Up to 9 Outstanding Read command allowed)</li>
</ul>
</li>
</ul>
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<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>To use timers timeout value Timeout enable field should be enabled. Users should check for the status of existing transfers before making configuration changes. </dd></dl>

<p>References <a class="el" href="struct_x_csu_dma___configure.html#a984f69d8fa925618e85800ba8fd2d155">XCsuDma_Configure::Acache</a>, <a class="el" href="struct_x_csu_dma___configure.html#a7ca88dbe204c7b24ce7e529da53e1ae2">XCsuDma_Configure::ApbErr</a>, <a class="el" href="struct_x_csu_dma___configure.html#a1aeadd99f4f96da636b9cb0c2be21c09">XCsuDma_Configure::AxiBurstType</a>, <a class="el" href="struct_x_csu_dma___config.html#a85e9f7798c5aa5ad4fbc9a8d0ba62990">XCsuDma_Config::BaseAddress</a>, <a class="el" href="struct_x_csu_dma.html#ab64e65f366955cbbc63436336de5ac48">XCsuDma::Config</a>, <a class="el" href="struct_x_csu_dma___configure.html#a4d1217d471a558f54534c15213bbb264">XCsuDma_Configure::EndianType</a>, <a class="el" href="struct_x_csu_dma___configure.html#af17af84045f926ff8e386509cc0c9aee">XCsuDma_Configure::FifoThresh</a>, <a class="el" href="struct_x_csu_dma.html#ab458e2393e0b44a976037f496de9e679">XCsuDma::IsReady</a>, <a class="el" href="struct_x_csu_dma___configure.html#acdf6a30da74f891648e17d1ce9bfadae">XCsuDma_Configure::MaxOutCmds</a>, <a class="el" href="struct_x_csu_dma___configure.html#ac6f8c811d5b1ecf86d37091fc132717e">XCsuDma_Configure::RouteBit</a>, <a class="el" href="struct_x_csu_dma___configure.html#a524260e03c75bc8745da0e4b7dca71ed">XCsuDma_Configure::SssFifoThesh</a>, <a class="el" href="struct_x_csu_dma___configure.html#a2f45ba702e0487ed32152186339d7052">XCsuDma_Configure::TimeoutEn</a>, <a class="el" href="struct_x_csu_dma___configure.html#a00365f4d0973fcb3fd39382312775748">XCsuDma_Configure::TimeoutPre</a>, <a class="el" href="struct_x_csu_dma___configure.html#af2b9f211561ad313b726a60104afc32e">XCsuDma_Configure::TimeoutValue</a>, <a class="el" href="group__csuma__api.html#ga60d1ed5209af6a5d9e9c55b6b95052de">XCSUDMA_CTRL_OFFSET</a>, <a class="el" href="group__csuma__api.html#gga46008337fdd632f2650b8727c305eba5a08d300b013b7169bd1475fdf04737fe4">XCSUDMA_DST_CHANNEL</a>, <a class="el" href="group__csuma__api.html#ga356d29aa2d43a1b724700007be7dcd51">XCsuDma_ReadReg</a>, <a class="el" href="group__csuma__api.html#gga46008337fdd632f2650b8727c305eba5afe0a7c4c64751afddad37c4a15a00e0d">XCSUDMA_SRC_CHANNEL</a>, and <a class="el" href="group__csuma__api.html#ga5a2390fe93e02061d01c3b9e057b3b2b">XCsuDma_WriteReg</a>.</p>

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          <td class="memname">void XCsuDma_Transfer </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__csuma__api.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a>&#160;</td>
          <td class="paramname"><em>Channel</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u64&#160;</td>
          <td class="paramname"><em>Addr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Size</em>, </td>
        </tr>
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          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>EnDataLast</em>&#160;</td>
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          <td></td>
          <td>)</td>
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<p>This function sets the starting address and size of the data to be transferred from/to the memory through the AXI interface. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>Pointer to <a class="el" href="struct_x_csu_dma.html" title="The XCsuDma driver instance data structure. ">XCsuDma</a> instance to be worked on. </td></tr>
    <tr><td class="paramname">Channel</td><td>Type of channel Source channel - XCSUDMA_SRC_CHANNEL Destination Channel - XCSUDMA_DST_CHANNEL </td></tr>
    <tr><td class="paramname">Addr</td><td>64 bit variable which holds the starting address of data which needs to write into the memory(DST) (or read from the memory(SRC)). </td></tr>
    <tr><td class="paramname">Size</td><td>32 bit variable which represents the number of 4 byte words needs to be transferred from starting address. </td></tr>
    <tr><td class="paramname">EnDataLast</td><td>Triggers an end of the message. Enables or disables data_inp_last signal to stream interface when current command is completed. It is applicable only to source channel; ignored for destination channel.<ul>
<li>1 - Asserts data_inp_last signal.</li>
<li>0 - data_inp_last will not be asserted.</li>
</ul>
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<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>Data_inp_last signal is asserted simultaneously with the data_inp_valid signal associated with the final 32-bit word transfer. </dd></dl>

<p>References <a class="el" href="struct_x_csu_dma___config.html#a85e9f7798c5aa5ad4fbc9a8d0ba62990">XCsuDma_Config::BaseAddress</a>, <a class="el" href="struct_x_csu_dma.html#ab64e65f366955cbbc63436336de5ac48">XCsuDma::Config</a>, <a class="el" href="struct_x_csu_dma.html#ab458e2393e0b44a976037f496de9e679">XCsuDma::IsReady</a>, <a class="el" href="group__csuma__api.html#ga76fcd0f2a0c7ebc2058f231a944c7109">XCSUDMA_ADDR_OFFSET</a>, <a class="el" href="group__csuma__api.html#gga46008337fdd632f2650b8727c305eba5a08d300b013b7169bd1475fdf04737fe4">XCSUDMA_DST_CHANNEL</a>, <a class="el" href="group__csuma__api.html#gaf0a5114bb4e675c0e9d933a2d235ac6f">XCSUDMA_LAST_WORD_MASK</a>, <a class="el" href="xcsudma_8h.html#ab57550413ed1c53f70a33ad4b90965eb">XCSUDMA_SIZE_MAX</a>, <a class="el" href="group__csuma__api.html#gaf5d3e01cba7a5d0029901f690007a9c0">XCSUDMA_SIZE_OFFSET</a>, <a class="el" href="group__csuma__api.html#gae1d5689d4fbd05c2e7f6b2a34bcbfb09">XCSUDMA_SIZE_SHIFT</a>, <a class="el" href="group__csuma__api.html#gga46008337fdd632f2650b8727c305eba5afe0a7c4c64751afddad37c4a15a00e0d">XCSUDMA_SRC_CHANNEL</a>, <a class="el" href="group__csuma__api.html#gaf448568bb484f8b80052682f399f194d">XCSUDMA_WORD_SIZE</a>, and <a class="el" href="group__csuma__api.html#ga5a2390fe93e02061d01c3b9e057b3b2b">XCsuDma_WriteReg</a>.</p>

<p>Referenced by <a class="el" href="xcsudma__intr__example_8c.html#ae07b94c3ade7479c4ec8dfec3bb4d643">XCsuDma_IntrExample()</a>, and <a class="el" href="xcsudma__polled__example_8c.html#aff327ee48af8d9e5c4018dd4e463674c">XCsuDma_PolledExample()</a>.</p>

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          <td class="memname">u32 XCsuDma_WaitForDoneTimeout </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_csu_dma.html">XCsuDma</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__csuma__api.html#ga46008337fdd632f2650b8727c305eba5">XCsuDma_Channel</a>&#160;</td>
          <td class="paramname"><em>Channel</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
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<p>This function polls for completion of data transfer periodically until the DMA done bit set or until the timeout occurs. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>Pointer to <a class="el" href="struct_x_csu_dma.html" title="The XCsuDma driver instance data structure. ">XCsuDma</a> instance to be worked on. </td></tr>
    <tr><td class="paramname">Channel</td><td>Type of channel Source channel - XCSUDMA_SRC_CHANNEL Destination Channel - XCSUDMA_DST_CHANNEL</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>XST_SUCCESS - In case of Success XST_FAILURE - In case of Timeout.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_csu_dma___config.html#a85e9f7798c5aa5ad4fbc9a8d0ba62990">XCsuDma_Config::BaseAddress</a>, <a class="el" href="struct_x_csu_dma.html#ab64e65f366955cbbc63436336de5ac48">XCsuDma::Config</a>, <a class="el" href="group__csuma__api.html#ga0bd0c9763013ce910920b46ad35d10ba">XCSUDMA_DONE_TIMEOUT_VAL</a>, <a class="el" href="group__csuma__api.html#gga46008337fdd632f2650b8727c305eba5a08d300b013b7169bd1475fdf04737fe4">XCSUDMA_DST_CHANNEL</a>, <a class="el" href="group__csuma__api.html#gab56adb100901bb2b042a842619064ce5">XCSUDMA_I_STS_OFFSET</a>, <a class="el" href="group__csuma__api.html#ga0dbd333c70de601e769b8542552eb7e4">XCSUDMA_IXR_DONE_MASK</a>, and <a class="el" href="group__csuma__api.html#gga46008337fdd632f2650b8727c305eba5afe0a7c4c64751afddad37c4a15a00e0d">XCSUDMA_SRC_CHANNEL</a>.</p>

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